Golden model
Python reference simulator for checking arithmetic and functional behavior.
Updated 28 September 2026
Development progress
ZilionX is an active engineering project. Milestones below distinguish implemented and measured work from current development and planned evaluation.
Completed
RTL components
Fixed-point arithmetic, attention and softmax work with component-level verification.
Transformer datapath
Integrated attention, normalization, residual and feed-forward paths. An eight-layer simulation baseline recorded 31,906 cycles for its defined test configuration.
In development
Stage 3M
Memory fabric
Work began in September 2026. The design is being shaped by the baseline cycle breakdown and will be assessed using direct measurements of memory transactions, stalls, conflicts and compute utilisation. No Stage 3M performance improvement is claimed yet.
Planned
FPGA evaluation
Implement and measure the design on an FPGA, including timing closure, memory and logic resources, and power where measurable.
Representative workloads
Move from the current small test configuration toward compact language Transformer workloads and, later, Vision Transformer inference.
Developer integration
Build an evaluation path and minimal software interface after the hardware baseline is stable.